According to the International Technology Roadmap for Semiconductors, the spectacular CMOS technology scaling will continue to evolve and dominate the semiconductor industry for another 10 years. This will lead to over 14 billion transistors integrated on a single chip by the year 2018. Such a scaling has already created a large design productivity gap due to inherent design complexities and deep submicron issues. Meanwhile, development cost, including both the design cost and manufacturing cost, of integrated circuits has grown significantly given the increasing size of the design team and the lengthy design cycles. Both problems, if not addressed, will be the red brick walls on the technology roadmap. Some key solutions for managing the exponential increase of the design complexity are the development of more scalable optimization engines, higher level of design abstraction, and design reuse. Some key solutions for controlling the increase in manufacturing cost are design for manufacturing, use of alternative silicon implementation platforms, and silicon reuse. In this context, the research group led by Prof. Chen will mainly pursue the following research directions: system-level and high-level synthesis, design space exploration for system-on-chip, reconfigurable computing, GPU computing and optimization, and the design of novel computing platforms, including FPGAs with nanotechnology.
Ph.D. in Computer Science, University of California at Los Angeles, Los Angeles, California, 2005